{"title":"高K/Ge和III-V基栅极堆的氧化物缺陷和可靠性","authors":"J. Robertson, Yuzheng Guo","doi":"10.1109/IIRW.2015.7437063","DOIUrl":null,"url":null,"abstract":"To date, gate stacks for high mobility semiconductors like Ge and InGaAs have been generally designed to minimise their interfacial trap density, and thus include an Al oxide layer diffusion barrier as a component. However, this is now known to lead to reduced reliability. The source of the problem is discussed and possible solutions based on an AlN or AlON layer component are suggested instead. First, we discuss traps in HfO2-based Si gate stacks and their reliability.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Oxide defects and reliability of high K/Ge and III–V based gate stacks\",\"authors\":\"J. Robertson, Yuzheng Guo\",\"doi\":\"10.1109/IIRW.2015.7437063\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"To date, gate stacks for high mobility semiconductors like Ge and InGaAs have been generally designed to minimise their interfacial trap density, and thus include an Al oxide layer diffusion barrier as a component. However, this is now known to lead to reduced reliability. The source of the problem is discussed and possible solutions based on an AlN or AlON layer component are suggested instead. First, we discuss traps in HfO2-based Si gate stacks and their reliability.\",\"PeriodicalId\":120239,\"journal\":{\"name\":\"2015 IEEE International Integrated Reliability Workshop (IIRW)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE International Integrated Reliability Workshop (IIRW)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IIRW.2015.7437063\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Integrated Reliability Workshop (IIRW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IIRW.2015.7437063","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Oxide defects and reliability of high K/Ge and III–V based gate stacks
To date, gate stacks for high mobility semiconductors like Ge and InGaAs have been generally designed to minimise their interfacial trap density, and thus include an Al oxide layer diffusion barrier as a component. However, this is now known to lead to reduced reliability. The source of the problem is discussed and possible solutions based on an AlN or AlON layer component are suggested instead. First, we discuss traps in HfO2-based Si gate stacks and their reliability.