在新的模拟BIST结构中实现一个BIC监视器

M. Sidiropulos, V. Stopjaková, H. Manhaeve
{"title":"在新的模拟BIST结构中实现一个BIC监视器","authors":"M. Sidiropulos, V. Stopjaková, H. Manhaeve","doi":"10.1109/IDDQ.1996.557817","DOIUrl":null,"url":null,"abstract":"The last step in the development of a BIST structure employing a new self-test technique for analog circuits is presented in this paper, namely the design and implementation of a suitable built-in supply current (BIC) monitor. The new self-test technique based on power supply current monitoring, takes advantage of the redundancy in the structure of fully balanced circuits. The new technique requires a special BIC monitor that provides appropriate signals for a successful fault detection. The BIC monitor, presented in this paper, is based on a second generation current conveyor CCII+, and offers an accurate measurement of supply currents with a minimal supply voltage degradation. The BIC monitor circuit was evaluated using fault simulations, which show a reasonable fault coverage. An implementation of the new BIC monitor in an analog BIST structure is finally described.","PeriodicalId":285207,"journal":{"name":"Digest of Papers 1996 IEEE International Workshop on IDDQ Testing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Implementation of a BIC monitor in a new analog BIST structure\",\"authors\":\"M. Sidiropulos, V. Stopjaková, H. Manhaeve\",\"doi\":\"10.1109/IDDQ.1996.557817\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The last step in the development of a BIST structure employing a new self-test technique for analog circuits is presented in this paper, namely the design and implementation of a suitable built-in supply current (BIC) monitor. The new self-test technique based on power supply current monitoring, takes advantage of the redundancy in the structure of fully balanced circuits. The new technique requires a special BIC monitor that provides appropriate signals for a successful fault detection. The BIC monitor, presented in this paper, is based on a second generation current conveyor CCII+, and offers an accurate measurement of supply currents with a minimal supply voltage degradation. The BIC monitor circuit was evaluated using fault simulations, which show a reasonable fault coverage. An implementation of the new BIC monitor in an analog BIST structure is finally described.\",\"PeriodicalId\":285207,\"journal\":{\"name\":\"Digest of Papers 1996 IEEE International Workshop on IDDQ Testing\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-10-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Papers 1996 IEEE International Workshop on IDDQ Testing\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IDDQ.1996.557817\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Papers 1996 IEEE International Workshop on IDDQ Testing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IDDQ.1996.557817","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10

摘要

本文介绍了采用新的模拟电路自测技术开发BIST结构的最后一步,即设计和实现一个合适的内置电源电流监视器。基于电源电流监测的自检技术,充分利用了全平衡电路结构的冗余性。新技术需要一种特殊的BIC监视器,为成功的故障检测提供适当的信号。本文提出的BIC监测器基于第二代电流输送机CCII+,可以在最小的电源电压退化的情况下精确测量电源电流。通过故障仿真对BIC监控电路进行了评估,显示出了合理的故障覆盖率。最后描述了在模拟BIST结构中实现新的BIC监视器。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Implementation of a BIC monitor in a new analog BIST structure
The last step in the development of a BIST structure employing a new self-test technique for analog circuits is presented in this paper, namely the design and implementation of a suitable built-in supply current (BIC) monitor. The new self-test technique based on power supply current monitoring, takes advantage of the redundancy in the structure of fully balanced circuits. The new technique requires a special BIC monitor that provides appropriate signals for a successful fault detection. The BIC monitor, presented in this paper, is based on a second generation current conveyor CCII+, and offers an accurate measurement of supply currents with a minimal supply voltage degradation. The BIC monitor circuit was evaluated using fault simulations, which show a reasonable fault coverage. An implementation of the new BIC monitor in an analog BIST structure is finally described.
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