CMOS mixed digital analog reconfigurable neural network with Gaussian synapses

In the neuromorphic arena, different engineering problems require different neural network topologies. In view of this concept, the motivation was to build a reconfigurable neural network chip. The distributed Gaussian-neuron synapse is introduced as a new type of synapses. Also a new improved resolution current-mode winner-takes-all circuit is added to realize a self-organizing topology. The chip is organized into 4 partially connected tiles with 4/spl times/3 fully connected neurons per tile. The chip was fabricated through MOSIS in 1.2 /spl mu/m AMI CMOS process occupying an area of 2 mm /spl times/2 mm.