具有高带宽、高延迟互连网络的多处理器系统上处理元件的设计

[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track Pub Date : 1989-01-03 DOI:10.1109/HICSS.1989.47173

R. Kenner, S. Dickey, P. Teller

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引用次数: 4

摘要

描述了高度并行、高延迟互连网络环境与单处理器系统环境的不同之处。讨论了这些差异对加工元件设计的影响。研究了可用于评估架构选择对使用类似网络的任何系统性能的影响的方法。以使用CISC(复杂指令集计算机)处理器和RISC(精简指令集计算机)处理器的两种处理元件的详细设计为例。

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The design of processing elements on a multiprocessor system with a high-bandwidth, high-latency interconnection network

A description is given of the ways in which the environment of a highly parallel, high-latency interconnection network is different from that encountered in a uniprocessor system. The impact of these differences on the design of the processing elements is discussed. Methods that can be used to evaluate the impact of architectural choices on the performance of any system that uses a similar network are examined. Two detailed designs of processing elements, one using a CISC (complex-instruction-set computer) processor and the other using a RISC (reduced-instruction-set computer) are given as examples.<>

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[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track

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