结合IEEE标准1149.1和减少引脚数组件测试

Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's Pub Date : 1991-04-15 DOI:10.1109/VTEST.1991.208137

S. F. Oakland

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引用次数: 3

摘要

本文描述了一种边界扫描结构，该结构允许使用相对便宜的降低引脚数自动测试设备(ATE)对具有高信号输入/输出(I/O)引脚数的电平敏感扫描设计(LSSD)组件进行全面测试。此外，该结构符合IEEE标准1149.1，测试访问端口和边界扫描架构，简化了组装印刷电路板或其他多组件基板的测试。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Combining IEEE Standard 1149.1 with reduced-pin-count component test

This paper describes a boundary-scan structure that permits comprehensive testing of level-sensitive-scan design (LSSD) components with high signal input/output (I/O) pin counts, using relatively inexpensive reduced-pin-count automatic testing equipment (ATE). Furthermore, the structure conforms to IEEE Standard 1149.1, Test Access Port and Boundary-Scan Architecture, which simplifies testing of assembled printed-circuit boards or other multi-component substrates.<>

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来源期刊

Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's

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