Learning-Based Reconfigurable Cache for Heterogeneous Chip Multiprocessors

In this work, a new energy-efficient reconfigurable cache architecture for chip multiprocessors is proposed. We formulate the reconfiguration problem based on using a machine learning technique. The proposed approach predicts the latency of the last-level cache in the next interval and then detects the type of it at runtime. This work provides a new approach that uses a neural network algorithm to reconfigure cache components. Experimental results show that the proposed design improves energy consumption of a three-dimensional chip multiprocessor with 16 cores by about 45% and performance by about 13% in compared to non-reconfigurable baselines.