{"title":"VLSI实现离散小波变换","authors":"A. Grzeszczak, M. Mandal, S. Panchanathan","doi":"10.1109/CCECE.1995.526421","DOIUrl":null,"url":null,"abstract":"This paper presents a VLSI implementation of discrete wavelet transform (DWT). The architecture is systolic in nature and performs both high-pass and low-pass coefficient calculations with only one set of multipliers. The architecture is simple, modular, and cascadable, and has been implemented in VLSI. Simulation results show that real-time coefficient calculation on a 512/spl times/612 pixels monochrome video input can be achieved.","PeriodicalId":158581,"journal":{"name":"Proceedings 1995 Canadian Conference on Electrical and Computer Engineering","volume":"530 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"141","resultStr":"{\"title\":\"VLSI implementation of discrete wavelet transform\",\"authors\":\"A. Grzeszczak, M. Mandal, S. Panchanathan\",\"doi\":\"10.1109/CCECE.1995.526421\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a VLSI implementation of discrete wavelet transform (DWT). The architecture is systolic in nature and performs both high-pass and low-pass coefficient calculations with only one set of multipliers. The architecture is simple, modular, and cascadable, and has been implemented in VLSI. Simulation results show that real-time coefficient calculation on a 512/spl times/612 pixels monochrome video input can be achieved.\",\"PeriodicalId\":158581,\"journal\":{\"name\":\"Proceedings 1995 Canadian Conference on Electrical and Computer Engineering\",\"volume\":\"530 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-09-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"141\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 1995 Canadian Conference on Electrical and Computer Engineering\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CCECE.1995.526421\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 1995 Canadian Conference on Electrical and Computer Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CCECE.1995.526421","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper presents a VLSI implementation of discrete wavelet transform (DWT). The architecture is systolic in nature and performs both high-pass and low-pass coefficient calculations with only one set of multipliers. The architecture is simple, modular, and cascadable, and has been implemented in VLSI. Simulation results show that real-time coefficient calculation on a 512/spl times/612 pixels monochrome video input can be achieved.