可靠处理系统的自适应单事件效应缓解

R. Glein, F. Rittner, A. Heuberger
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引用次数: 3

摘要

对于在辐射恶劣环境中的应用,设计师根据最坏情况(太阳能)条件应用缓解技术,以实现可靠的设计。这将导致资源开销,而这在大多数情况下是不必要的。为了克服这个问题,使用了自适应缓解技术。该技术是在性能和可靠性等两个参数之间进行权衡,根据不同的操作模式在这些模式之间切换。在此背景下,我们提出了一种自适应单事件效应缓解(ASEEM)方法。它基于FPGA在两种模式之间的自适应重构,特别是性能模式和高可靠性模式。性能模式提供高处理能力,从而提高信号处理吞吐量。我们通过对一个空间级和两个商业级fpga从2010年到2016年的粒子数据计算结果来评估ASEEM。根据辐射数据,我们计算出了拆迁率、可用性、性能和性能。我们详细讨论了一种具有固定扰流率的ASEEM实现。本文给出的例子表明,在考虑的时间间隔内,搅乱率从六分之一降低到九分之一(与性能模式相比),高处理能力的可用性超过90%。我们得出结论,所研究的ASEEM实现对于中等和较长的平均修复时间是最佳的。在处理案例研究中,在固定的平均修复时间为一小时的情况下,我们获得了使用最新半导体技术的FPGA性能模式的14%的性能改进和21%的可用性改进。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Adaptive single-event effect mitigation for dependable processing systems
For application in radiation-harsh environments, designers apply mitigation techniques according the worst-case (solar) condition to achieve a dependable design. This results in a resource overhead, which is most of the time unnecessary. To overcome this problem, adaptive mitigation techniques are used. This technique is a trade-off between two parameters, such as performance and reliability, according to different operating modes by toggling between these modes. In this context, we propose an Adaptive Single-Event Effect Mitigation (ASEEM) method. It is based on adaptive reconfiguration of an FPGA between two modes, specifically a performance mode and a high reliability mode. The performance mode offers high processing power and thus higher signal processing throughput. We evaluate ASEEM by calculating results with particle data from 2010 until 2016 for one space-grade and two commercial-grade FPGAs. Based on radiation data, we calculate upset rates, availability, performance and performability. We discuss one realization of ASEEM in detail with fixed upset rates. The examples presented in this paper show a reduction of the upset rate form a sixth to a ninth (compared with the performance mode) and the availability of the high processing power over 90 % in the considered time interval. We conclude that the investigated ASEEM realization is optimal for moderate and long mean times to repair. In a processing case study, with a fixed mean time to repair of one hour, we obtain a performability improvement of 14% and an availability improvement of 21 % over the performance mode for an FPGA using the latest semiconductor technology.
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