带VSS发生器的快速访问BiCMOS SRAM架构

Digest of Technical Papers., 1990 Symposium on VLSI Circuits Pub Date : 1990-06-07 DOI:10.1109/VLSIC.1990.111087

T. Douseki, Y. Ohmori, H. Yoshino, J. Yamada

{"title":"带VSS发生器的快速访问BiCMOS SRAM架构","authors":"T. Douseki, Y. Ohmori, H. Yoshino, J. Yamada","doi":"10.1109/VLSIC.1990.111087","DOIUrl":null,"url":null,"abstract":"A fast-access intermediate supply voltage level BiCMOS SRAM (ISVOL) architecture is proposed for advancing circuit technology to megabit-level SRAMs using low-submicron MOSFETs. To verify this concept's effectiveness, a 256-kb SRAM, with a typical access time of 5 ns, is evaluated and reported. The access time dependence of the supply voltage is shown. This architecture can suppress the access time variance to within 4% for a 15% supply voltage variation","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"Fast-access BiCMOS SRAM architecture with a VSS generator\",\"authors\":\"T. Douseki, Y. Ohmori, H. Yoshino, J. Yamada\",\"doi\":\"10.1109/VLSIC.1990.111087\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A fast-access intermediate supply voltage level BiCMOS SRAM (ISVOL) architecture is proposed for advancing circuit technology to megabit-level SRAMs using low-submicron MOSFETs. To verify this concept's effectiveness, a 256-kb SRAM, with a typical access time of 5 ns, is evaluated and reported. The access time dependence of the supply voltage is shown. This architecture can suppress the access time variance to within 4% for a 15% supply voltage variation\",\"PeriodicalId\":239990,\"journal\":{\"name\":\"Digest of Technical Papers., 1990 Symposium on VLSI Circuits\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-06-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Technical Papers., 1990 Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1990.111087\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1990.111087","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 15

摘要

提出了一种快速存取的中间电源电压级BiCMOS SRAM (ISVOL)架构，利用低亚微米mosfet将电路技术提升到兆位级SRAM。为了验证这一概念的有效性，评估和报告了一个256 kb的SRAM，典型的访问时间为5 ns。供电电压与接入时间的关系如图所示。这种结构可以在电源电压变化15%的情况下将接入时间方差抑制在4%以内

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Fast-access BiCMOS SRAM architecture with a VSS generator

A fast-access intermediate supply voltage level BiCMOS SRAM (ISVOL) architecture is proposed for advancing circuit technology to megabit-level SRAMs using low-submicron MOSFETs. To verify this concept's effectiveness, a 256-kb SRAM, with a typical access time of 5 ns, is evaluated and reported. The access time dependence of the supply voltage is shown. This architecture can suppress the access time variance to within 4% for a 15% supply voltage variation

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Digest of Technical Papers., 1990 Symposium on VLSI Circuits

自引率

0.00%

发文量