K. Vijayakumar, R. A. Kumar, A. Govindasamy, S. Kannan
{"title":"矩阵变换器正弦脉宽调制的FPGA实现","authors":"K. Vijayakumar, R. A. Kumar, A. Govindasamy, S. Kannan","doi":"10.1109/ICCSP.2014.6949971","DOIUrl":null,"url":null,"abstract":"The purpose of this paper is to develop the Sinusoidal Pulse Width Modulation (SPWM) for toggling the switches of Matrix Converter for its operation as several Power Electronics Converters. The SPWM generation is developed with the help of Quartus based Field Programmable Gate Array (FPGA). Quartus II is a software tool produced by Altera for analysis and synthesis of HDL design which enables the developer to compile their designs. Quartus II software includes all the design files, software source files and other related files necessary for the eventual implementation of a design in Programmable Logic Devices. SPWM provides a way to reduce the Total Harmonic Distortion (THD) of load current. The VHDL programming is used to generate the SPWM for switches. Simulation waveforms are obtained and the output of SPWM generation is developed with the help of the FPGA and the output is displayed in the CRO.","PeriodicalId":149965,"journal":{"name":"2014 International Conference on Communication and Signal Processing","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2014-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Implementation of Sinusoidal Pulse Width Modulation for Matrix Converter using FPGA\",\"authors\":\"K. Vijayakumar, R. A. Kumar, A. Govindasamy, S. Kannan\",\"doi\":\"10.1109/ICCSP.2014.6949971\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The purpose of this paper is to develop the Sinusoidal Pulse Width Modulation (SPWM) for toggling the switches of Matrix Converter for its operation as several Power Electronics Converters. The SPWM generation is developed with the help of Quartus based Field Programmable Gate Array (FPGA). Quartus II is a software tool produced by Altera for analysis and synthesis of HDL design which enables the developer to compile their designs. Quartus II software includes all the design files, software source files and other related files necessary for the eventual implementation of a design in Programmable Logic Devices. SPWM provides a way to reduce the Total Harmonic Distortion (THD) of load current. The VHDL programming is used to generate the SPWM for switches. Simulation waveforms are obtained and the output of SPWM generation is developed with the help of the FPGA and the output is displayed in the CRO.\",\"PeriodicalId\":149965,\"journal\":{\"name\":\"2014 International Conference on Communication and Signal Processing\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-04-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 International Conference on Communication and Signal Processing\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCSP.2014.6949971\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 International Conference on Communication and Signal Processing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCSP.2014.6949971","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Implementation of Sinusoidal Pulse Width Modulation for Matrix Converter using FPGA
The purpose of this paper is to develop the Sinusoidal Pulse Width Modulation (SPWM) for toggling the switches of Matrix Converter for its operation as several Power Electronics Converters. The SPWM generation is developed with the help of Quartus based Field Programmable Gate Array (FPGA). Quartus II is a software tool produced by Altera for analysis and synthesis of HDL design which enables the developer to compile their designs. Quartus II software includes all the design files, software source files and other related files necessary for the eventual implementation of a design in Programmable Logic Devices. SPWM provides a way to reduce the Total Harmonic Distortion (THD) of load current. The VHDL programming is used to generate the SPWM for switches. Simulation waveforms are obtained and the output of SPWM generation is developed with the help of the FPGA and the output is displayed in the CRO.