可扩展的目标检测加速器在fpga上使用定制设计空间探索

Chen-Chun Huang, F. Vahid
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引用次数: 12

摘要

我们讨论了使用基于精确haar特征的算法在视频流中实现对象(如人脸)检测器的FPGA。我们不是为一个FPGA创建一个实现,而是开发一种方法来生成一系列具有不同尺寸和性能的实现,以针对不同的FPGA设备。通过对与用于支持不同数量图像分类器的通信体系结构相关的特定设计问题进行自定义设计空间探索,可以实现自动生成。探索算法利用每个特征集中的内容信息来优化和生成可扩展的通信体系结构。我们为Xilinx Virtex5 LX50T、LX110T和LX155T FPGA设备生成了完全工作的实现,使用了不同数量的可用设备容量,与3.0 GHz的Pentium 4台式机相比,速度提高了0.6倍到25倍。在创建硬件加速器时,包括定制设计空间探索的自动生成器可能变得更加必要,这些硬件加速器旨在用于广泛的现有和未来的FPGA设备。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Scalable object detection accelerators on FPGAs using custom design space exploration
We discuss FPGA implementations of object (such as face) detectors in video streams using the accurate Haar-feature based algorithm. Rather than creating one implementation for one FPGA, we develop a method to generate a series of implementations that have different size and performance to target different FPGA devices. The automatic generation was enabled by custom design space exploration on a particular design problem relating to the communication architecture used to support different numbers of image classifiers. The exploration algorithm uses content information in each feature set to optimize and generate a scalable communication architecture. We generated fully-working implementations for Xilinx Virtex5 LX50T, LX110T, and LX155T FPGA devices, using various amounts of available device capacity, leading to speedups ranging from 0.6x to 25x compared to a 3.0 GHz Pentium 4 desktop machine. Automated generators that include custom design space exploration may become more necessary when creating hardware accelerators intended for use across a wide range of existing and future FPGA devices.
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