{"title":"传输极特性对k波段VCOs相位降噪的影响","authors":"Nusrat Jahan, A. Barakat, R. Pokharel","doi":"10.23919/apmc55665.2022.9999956","DOIUrl":null,"url":null,"abstract":"In this paper, effectiveness of multi-resonance around the parallel resonance of an LC-tank circuit on the reduction of K-band Voltage-Controlled Oscillators (VCOs) phase noise is proposed. The skirt characteristics of the Scattering $(\\vert \\mathrm{S}\\vert)$ parameters of the resonators is sharpened by introducing transmission poles beside the parallel resonance of the LC-tank circuit. In return, an enhanced the resonator loaded quality (Q) factor without compromising the unloaded Q-factor is obtained. Three designs are realized, verified and compared to the others in a differential VCO topology and the phase noise reduction in post-layout simulations is confirmed. Finally, two chips are fabricated in $0.18-\\upmu \\mathrm{m}$ CMOS technology and measured.","PeriodicalId":219307,"journal":{"name":"2022 Asia-Pacific Microwave Conference (APMC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Efficacy of Transmission Poles Characteristics on K-Band VCOs Phase Noise Reduction\",\"authors\":\"Nusrat Jahan, A. Barakat, R. Pokharel\",\"doi\":\"10.23919/apmc55665.2022.9999956\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, effectiveness of multi-resonance around the parallel resonance of an LC-tank circuit on the reduction of K-band Voltage-Controlled Oscillators (VCOs) phase noise is proposed. The skirt characteristics of the Scattering $(\\\\vert \\\\mathrm{S}\\\\vert)$ parameters of the resonators is sharpened by introducing transmission poles beside the parallel resonance of the LC-tank circuit. In return, an enhanced the resonator loaded quality (Q) factor without compromising the unloaded Q-factor is obtained. Three designs are realized, verified and compared to the others in a differential VCO topology and the phase noise reduction in post-layout simulations is confirmed. Finally, two chips are fabricated in $0.18-\\\\upmu \\\\mathrm{m}$ CMOS technology and measured.\",\"PeriodicalId\":219307,\"journal\":{\"name\":\"2022 Asia-Pacific Microwave Conference (APMC)\",\"volume\":\"20 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-11-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 Asia-Pacific Microwave Conference (APMC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/apmc55665.2022.9999956\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 Asia-Pacific Microwave Conference (APMC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/apmc55665.2022.9999956","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Efficacy of Transmission Poles Characteristics on K-Band VCOs Phase Noise Reduction
In this paper, effectiveness of multi-resonance around the parallel resonance of an LC-tank circuit on the reduction of K-band Voltage-Controlled Oscillators (VCOs) phase noise is proposed. The skirt characteristics of the Scattering $(\vert \mathrm{S}\vert)$ parameters of the resonators is sharpened by introducing transmission poles beside the parallel resonance of the LC-tank circuit. In return, an enhanced the resonator loaded quality (Q) factor without compromising the unloaded Q-factor is obtained. Three designs are realized, verified and compared to the others in a differential VCO topology and the phase noise reduction in post-layout simulations is confirmed. Finally, two chips are fabricated in $0.18-\upmu \mathrm{m}$ CMOS technology and measured.
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