All-inversion region gm/ID methodology for RF circuits in FinFET technologies

In the context of IoT applications, together with the use of deep-submicron technologies as FinFET, this paper presents a revision of the gm/ID methodology for radio-frequency analog front-end circuits. Particularly, this methodology is applied for the design of LC-VCOs in the 5.8-GHz band using 20-nm FinFET transistors. To incorporate the FinFET model into the design flow, a semi-empirical model is extracted from electrical simulations. To show the good performance of the methodology, an LC-VCO design, picked from the calculated design maps, is electrically simulated, achieving good match regarding oscillation frequency and phase noise.