SIFT Keypoint Descriptor Matching Algorithm: A Fully Pipelined Accelerator on FPGA(Abstract Only)

Scale Invariant Feature Transform (SIFT) algorithm is one of the classical feature extraction algorithms that is well known in Computer Vision. It consists of two stages: keypoint descriptor extraction and descriptor matching. SIFT descriptor matching algorithm is a computational intensive process. In this work, we present a design and implementation of a hardware core accelerator for the descriptor-matching algorithm on a field programmable gate array (FPGA). Our proposed hardware core architecture is able to cope with the memory bandwidth and hit the roofline performance model to achieve maximum throughput. The matching-core was implemented using Xilinx Vivado® EDA design suite on a Zynq®-based FPGA Development board. The proposed matching-core architecture is fully pipelined for 16-bit fixed-point operations and consists of five main submodules designed in Verilog, High Level Synthesis, and System Generator. The area resources were significantly reduced compared to the most recent matching-core implemented on hardware. While our proposed hardware accelerator matching-core was able to detect 98% matching-points compared to the software approach, it is 15.7 × faster.