An efficient hardware architecture of intra prediction in HEVC standard

In the near future, the high resolution 4K and 8K will become the more used in video applications. This resolution is well supported in the new HEVC standard. This paper proposes a novel parallel and high efficient hardware accelerator for the intra prediction block. This accelerator achieves a high speed treatment due to pipelined processing units and parallel shaped architecture. The complexity of memory access is also reduced thanks to the proposed design even a less increased power consumption. Results show, that the proposed architecture takes 20095 LUT and can reach 510 MHz of maximum frequency and is capable to support the throughput of 3840×2160 sequence at 90 frames per second.