一个新的12b 40毫秒/秒，低功耗，低面积流水线ADC视频模拟前端

PACRIM. 2005 IEEE Pacific Rim Conference on Communications, Computers and signal Processing, 2005. Pub Date : 2005-10-17 DOI:10.1109/PACRIM.2005.1517360

M. Mohajerin, Cheng Chen, E. Abdel-Raheem

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引用次数: 2

摘要

设计了一种12位、40 MS/s的流水线模数转换器(ADC)，采用0.18-/spl mu/m CMOS技术，单电源电压为1.8 V。与传统的全差分电压模式流水线ADC相比，所提出的ADC架构采用电流模式和电压模式级的组合，显著降低了功耗和面积。仿真结果表明，该ADC具有应用于视频模拟前端的潜力。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A new 12-b 40 ms/s, low-power, low-area pipeline ADC for video analog front ends

A 12-bit, 40 MS/s pipelined analog-to-digital converter (ADC) is designed in 0.18-/spl mu/m CMOS technology with 1.8 V single power supply. The proposed ADC architecture uses a combination of current-mode and voltage-mode stages to, significantly, reduce both power dissipation and area compared to conventional fully differential voltage-mode pipeline ADCs. Simulation results are provided and indicate that the proposed ADC has potential to be deployed in the video analog front-ends.

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来源期刊

PACRIM. 2005 IEEE Pacific Rim Conference on Communications, Computers and signal Processing, 2005.

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