High efficiency high reliability SiC MOSFET with monolithically integrated Schottky rectifier

A junction barrier controlled Schottky rectifier integrated silicon carbide MOSFET (SiC JMOS) is proposed in this paper, which merged a double implanted MOSFET (DMOS) and junction barrier controlled Schottky diode (JBS) in a monolithic SiC device without any additional process and area penalty. JMOS device in this work exhibits a lower reverse conduction voltage drop than conventional SiC DMOS. There is a 47% improvement on VSD. There's also superior in dynamic performances such like lower reverse recovery charge (Qrr) and maximum reverse recovery current (IRMax) due to characteristics of unipolar devices. As a result, JMOS is 54% lower in Qrr and 40% lower in IRMax. The integrated JBS could also prevent the potential failure caused by the transformation of dislocation defects into stacking faults due to the recombination of injected minority carriers when parasitic body diode in SiC MOSFET was turned on. In this work, we make characteristics comparison and build a testing platform to verify the efficiency and reliability improvement of SiC JMOS from conventional SiC DMOS. The experiment result shows that we could gain better system performance and reliability with less cost and higher power density.