一个1.2V 12位SAR ADC与一个两级放大器满量程差分动态比较器

2018 10th International Conference on Communications, Circuits and Systems (ICCCAS) Pub Date : 2018-12-01 DOI:10.1109/ICCCAS.2018.8769189

Shouping Li, Yang Guo, Yao Liu, Jianjun Chen, Qing Xu, Jizuo Zhang

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引用次数: 0

摘要

提出了一种基于功率效率电容式数模转换器(CDAC)和两级放大满量程差分动态比较器的12b 25MS/s逐次逼近寄存器模数转换器(SAR ADC)结构。一种三电平开关方案被用于实现最高的开关效率，同时仍然保持误差容限的对称性。采用130nm CMOS技术的原型实现在25MS/s下实现了70.1dB的SNDR，而1.2V电压电源的功耗为0.21mW，导致FoM为37.4fJ/转换步长。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 1.2V 12 Bits SAR ADC with a Two Stages Amplifier Full-scale Differential Dynamic Comparator

This paper put forward a 12-b 25MS/s Successive Approximation Register Analog-to-Digital Converter (SAR ADC) architecture based on power efficiency Capacitive Digital-to-Analog (CDAC) and a two stages amplifier full-scale differential dynamic comparator. A tri-level switching scheme is being used to achieve the highest switching efficiency while still conserving the symmetry in error tolerance. The prototype implementation in 130nm CMOS technology achieves a 70.1dB SNDR at 25MS/s, while dissipating 0.21mW from a 1.2V voltage supply, leading to a FoM of 37.4fJ/conversion-step.

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2018 10th International Conference on Communications, Circuits and Systems (ICCCAS)

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