A new state assignment method targeting FPGA implementations

State assignment is one of the most important problems in hardware implementation of finite state machines. It influences to a high degree all quality aspects of the final hardware implementation. FPGAs are commonly used for implementation of systems produced in small- to medium-size series or requiring a relatively high speed and/or (re)programmability. With both speed and logic capacity rapidly growing, FPGAs evolved very quickly to highly-flexible technology of choice for major manufacturers. Unfortunately, the progress in synthesis methods and EDA tools for FPGA implementations does not keep up with the revolutionary development of the FPGA hardware platform. The characteristic features of the technology invalidate the traditionally used criteria, heuristics and synthesis methods. The development of new FPGA-targeted (near) optimal state assignment methods is therefore of primary practical importance. In this paper we propose a new state assignment method for FPGA implementations. It consists in optimization of the information flows in the resulting circuit. This results in binary functions with compact input supports, circuit composed of reasonably independent and highly coherent parts, and minimized (long) interconnections between the parts. The proposed method produces therefore compact and fast circuits in FPGA technology. Our tool that implements the method, compared to state-of-the-art encoding tools, consistently produces high quality results.