{"title":"一个443µA 37.8 nv /√Hz CMOS多级带隙电压基准","authors":"W. Yan, T. Christen","doi":"10.1109/ESSCIRC.2013.6649080","DOIUrl":null,"url":null,"abstract":"A CMOS bandgap voltage reference is presented, which achieves a low integrated noise of 150nVrms within a 0.1-10Hz bandwidth and a 37.8nV/√Hz wideband noise floor above 100Hz. The low noise performance is accomplished by employing a multi-stage bandgap topology, which results in an inherent noise advantage compared to a conventional CMOS bandgap. Fabricated in a 0.35μm HV CMOS technology, the bandgap voltage reference consumes 443μA from a nominal 3.4-V supply and occupies 0.5mm2 chip area.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 443-µA 37.8-nV/√Hz CMOS multi-stage bandgap voltage reference\",\"authors\":\"W. Yan, T. Christen\",\"doi\":\"10.1109/ESSCIRC.2013.6649080\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A CMOS bandgap voltage reference is presented, which achieves a low integrated noise of 150nVrms within a 0.1-10Hz bandwidth and a 37.8nV/√Hz wideband noise floor above 100Hz. The low noise performance is accomplished by employing a multi-stage bandgap topology, which results in an inherent noise advantage compared to a conventional CMOS bandgap. Fabricated in a 0.35μm HV CMOS technology, the bandgap voltage reference consumes 443μA from a nominal 3.4-V supply and occupies 0.5mm2 chip area.\",\"PeriodicalId\":183620,\"journal\":{\"name\":\"2013 Proceedings of the ESSCIRC (ESSCIRC)\",\"volume\":\"117 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-10-31\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 Proceedings of the ESSCIRC (ESSCIRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2013.6649080\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 Proceedings of the ESSCIRC (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2013.6649080","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
摘要
提出了一种CMOS带隙基准电压，在0.1 ~ 10hz带宽范围内实现了150nVrms的低集成噪声，在100Hz以上实现了37.8nV/√Hz的宽带本底噪声。低噪声性能是通过采用多级带隙拓扑来实现的，这与传统的CMOS带隙相比具有固有的噪声优势。该带隙基准电压采用0.35μ v CMOS工艺，标称3.4 v电源功耗为443μA，芯片面积为0.5mm2。
A 443-µA 37.8-nV/√Hz CMOS multi-stage bandgap voltage reference
A CMOS bandgap voltage reference is presented, which achieves a low integrated noise of 150nVrms within a 0.1-10Hz bandwidth and a 37.8nV/√Hz wideband noise floor above 100Hz. The low noise performance is accomplished by employing a multi-stage bandgap topology, which results in an inherent noise advantage compared to a conventional CMOS bandgap. Fabricated in a 0.35μm HV CMOS technology, the bandgap voltage reference consumes 443μA from a nominal 3.4-V supply and occupies 0.5mm2 chip area.
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