Multichannel pipeline implementation of the correcting matrix in the fast cosine transform algorithm

In this paper methods of multichannel pipeline processors design for implementation of the fast cosine transform correcting matrix are considered. Three basic methods for the correcting matrix implementation are compared and a number of pipeline processors with their comparative estimation depending on performance, hardware amount and application are proposed. A new method of optimal hardware amount multichannel pipeline processors structure based on synthesis of three basic methods is proposed.