采用130纳米CMOS技术的1-V 24 ghz低压低功率电流模式发射器

Wen-Chieh Wang, Chung-Yu Wu
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引用次数: 11

摘要

为了实现24 GHz频段的发射机前端,提出了一种新型的高频CMOS电流模上变频混频器。发射器集成了一个双平衡电流模式上转换混频器,一个中频放大器/中继器,一个差分压控振荡器和一个差分压控振荡器缓冲器/中继器。发射机的转换增益为1.3 dB,输入1-dB压缩点(P-1db)为-22 dBm,输入截获三阶压缩点(PIIP3)为-8.75 dBm,输出截获三阶压缩点(POIP3)为-7.44 dBm。差分压控振荡器的相位噪声为-117 dBc/Hz。所提出的混频器仅消耗3.89兆瓦的1 v电源。发射机在1v供电时的总功耗为15.4 mW。该芯片采用0.13 μ m 1P8M CMOS技术设计,目前正在制造中。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
The 1-V 24-GHz low-voltage low-power current- mode transmitter in 130-nm CMOS technology
A new high frequency CMOS current-mode up-conversion mixer is proposed to realize the transmitter front-end in the frequency band of 24 GHz. The transmitter integrates with a double-balance current-mode up-conversion mixer, an IF amplifier/repeater, a differential VCO and a differential VCO buffer/repeater. The performance of the transmitter exhibits a conversion gain of 1.3 dB, the input 1-dB compression point (P-1db) is -22 dBm, the input intercept 3rd-order compression point (PIIP3) is -8.75 dBm, and the output intercept 3rd-order compression point (POIP3) is -7.44 dBm. The phase noise of the differential VCO is -117 dBc/Hz at 10-MHz offset from 26 GHz. The proposed mixer consumes only 3.89 mW from a 1-V supply. The total power dissipation of the transmitter is 15.4 mW from 1-V supply. This chip is designed in 0.13-mum 1P8M CMOS technology and under fabrication.
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