{"title":"Cell/B.E.短矢量SIMD处理器上最小加代数的矩阵乘加","authors":"Kazuya Matsumoto, S. Sedukhin","doi":"10.1109/IC-NC.2010.29","DOIUrl":null,"url":null,"abstract":"It is well-known that the all-pairs shortest paths problem has a similar algorithmic characteristic to the classical matrix-matrix multiply-add (MMA) problem, one of the differences between the two problems is in the underlying algebra: the matrix multiply-add uses linear (+, x)-algebra whereas the all-pairs shortest paths problem uses (min, +)-algebra. This paper presents an implementation of 64×64 matrix multiply-add kernel in (min, +)-algebra on a short-vector SIMD processor, the so-called Synergistic Processing Element (SPE), of the Cell Broadband Engine (Cell/B.E.). Our implementation for the shortest paths problem adopts an existing fast algorithm of matrix multiply-add with a reduction of the number of required registers. The MMA implementation in (min, +)-algebra achieves the speed of 8.502 Gflop/s, which is about three times as low as that of the (+, x)-algebra MMA and is very close to the theoretical estimation based on the required number of instructions.","PeriodicalId":375145,"journal":{"name":"2010 First International Conference on Networking and Computing","volume":"160 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Matrix Multiply-Add in Min-plus Algebra on a Short-Vector SIMD Processor of Cell/B.E.\",\"authors\":\"Kazuya Matsumoto, S. Sedukhin\",\"doi\":\"10.1109/IC-NC.2010.29\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"It is well-known that the all-pairs shortest paths problem has a similar algorithmic characteristic to the classical matrix-matrix multiply-add (MMA) problem, one of the differences between the two problems is in the underlying algebra: the matrix multiply-add uses linear (+, x)-algebra whereas the all-pairs shortest paths problem uses (min, +)-algebra. This paper presents an implementation of 64×64 matrix multiply-add kernel in (min, +)-algebra on a short-vector SIMD processor, the so-called Synergistic Processing Element (SPE), of the Cell Broadband Engine (Cell/B.E.). Our implementation for the shortest paths problem adopts an existing fast algorithm of matrix multiply-add with a reduction of the number of required registers. The MMA implementation in (min, +)-algebra achieves the speed of 8.502 Gflop/s, which is about three times as low as that of the (+, x)-algebra MMA and is very close to the theoretical estimation based on the required number of instructions.\",\"PeriodicalId\":375145,\"journal\":{\"name\":\"2010 First International Conference on Networking and Computing\",\"volume\":\"160 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-11-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 First International Conference on Networking and Computing\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IC-NC.2010.29\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 First International Conference on Networking and Computing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IC-NC.2010.29","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Matrix Multiply-Add in Min-plus Algebra on a Short-Vector SIMD Processor of Cell/B.E.
It is well-known that the all-pairs shortest paths problem has a similar algorithmic characteristic to the classical matrix-matrix multiply-add (MMA) problem, one of the differences between the two problems is in the underlying algebra: the matrix multiply-add uses linear (+, x)-algebra whereas the all-pairs shortest paths problem uses (min, +)-algebra. This paper presents an implementation of 64×64 matrix multiply-add kernel in (min, +)-algebra on a short-vector SIMD processor, the so-called Synergistic Processing Element (SPE), of the Cell Broadband Engine (Cell/B.E.). Our implementation for the shortest paths problem adopts an existing fast algorithm of matrix multiply-add with a reduction of the number of required registers. The MMA implementation in (min, +)-algebra achieves the speed of 8.502 Gflop/s, which is about three times as low as that of the (+, x)-algebra MMA and is very close to the theoretical estimation based on the required number of instructions.