High-level modelling and detection of the faulty behaviour of VOQ switches under balanced traffic

High-speed telecommunications routers are very important systems in today's networked environments. The purpose of this paper is to propose a mathematical model of the faulty behaviour of such systems and, derived from it, a scheme for the detection of errors occurring concurrently with their normal operation. Although the ultimate goal is to obtain a fault-tolerant router, this work concentrates on the scheduler part of the system and, in particular, in the case of virtual output-queued (VOQ) switches. As starting point, in this paper a balanced traffic load is assumed. The faulty behaviour of complex digital processing systems is usually better described at the algorithmic level, particularly when the operation of the system relies on complex mathematical principles. Therefore, the issues related to concurrent error detection are addressed from the developed mathematical model. Results are presented that point to the ability of the proposed solution to detect errors at a high abstraction level. They have been obtained by injecting faults in the algorithm flow rather than in the hardware itself.