{"title":"用于高分辨率adc的面积效率低功耗SC积分器","authors":"H. Zare-Hoseini, M. Azizi, O. Shoaei","doi":"10.1109/SCS.2003.1227065","DOIUrl":null,"url":null,"abstract":"In this paper, a very area-efficient low-noise low-power correlated double sampled integrator has been presented. A fully differential class AB op-amp with preamplifier is designed with gain of 85dB, bandwidth of 12 Mrad/s and overall input referred noise floor of -171 dB. For attenuating the integrator's op-amp thermal noise, the input transconductance is kept as large as needed and also the bandwidth of the op-amp is decreased as much as possible without the need for large compensation capacitors as in the ordinary topologies are used. The integrator is used in the front-end of a 24 bit, fourth-order single-loop Delta-Sigma modulator for a bandwidth of 1000 Rad/s. The integrator power consumption is only 2.8 mW with a single 3.0V supply in 0.6-μm CMOS technology.","PeriodicalId":375963,"journal":{"name":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An area-efficient low-power SC integrator for very high resolution ADCS\",\"authors\":\"H. Zare-Hoseini, M. Azizi, O. Shoaei\",\"doi\":\"10.1109/SCS.2003.1227065\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a very area-efficient low-noise low-power correlated double sampled integrator has been presented. A fully differential class AB op-amp with preamplifier is designed with gain of 85dB, bandwidth of 12 Mrad/s and overall input referred noise floor of -171 dB. For attenuating the integrator's op-amp thermal noise, the input transconductance is kept as large as needed and also the bandwidth of the op-amp is decreased as much as possible without the need for large compensation capacitors as in the ordinary topologies are used. The integrator is used in the front-end of a 24 bit, fourth-order single-loop Delta-Sigma modulator for a bandwidth of 1000 Rad/s. The integrator power consumption is only 2.8 mW with a single 3.0V supply in 0.6-μm CMOS technology.\",\"PeriodicalId\":375963,\"journal\":{\"name\":\"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on\",\"volume\":\"45 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-07-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SCS.2003.1227065\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SCS.2003.1227065","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An area-efficient low-power SC integrator for very high resolution ADCS
In this paper, a very area-efficient low-noise low-power correlated double sampled integrator has been presented. A fully differential class AB op-amp with preamplifier is designed with gain of 85dB, bandwidth of 12 Mrad/s and overall input referred noise floor of -171 dB. For attenuating the integrator's op-amp thermal noise, the input transconductance is kept as large as needed and also the bandwidth of the op-amp is decreased as much as possible without the need for large compensation capacitors as in the ordinary topologies are used. The integrator is used in the front-end of a 24 bit, fourth-order single-loop Delta-Sigma modulator for a bandwidth of 1000 Rad/s. The integrator power consumption is only 2.8 mW with a single 3.0V supply in 0.6-μm CMOS technology.
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