{"title":"StrongARM:高性能的ARM处理器","authors":"R. Witek, J. Montanaro","doi":"10.1109/CMPCON.1996.501767","DOIUrl":null,"url":null,"abstract":"A 32-bit 162 MHz/215 MHz custom VLSI ARM microprocessor is described. The chip contains two 16 Kbyte, 32-way set associative caches for instructions and data. The 2.1 M transistor chip is fabricated in a 2.0 V, 0.35 /spl mu/m, 3-layer metal CMOS process. It dissipates 0.5 W at 162 MHz/1.5 V and 1.1 W at 215 MHz/2.0 V.","PeriodicalId":117038,"journal":{"name":"COMPCON '96. Technologies for the Information Superhighway Digest of Papers","volume":"111 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":"{\"title\":\"StrongARM: a high-performance ARM processor\",\"authors\":\"R. Witek, J. Montanaro\",\"doi\":\"10.1109/CMPCON.1996.501767\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 32-bit 162 MHz/215 MHz custom VLSI ARM microprocessor is described. The chip contains two 16 Kbyte, 32-way set associative caches for instructions and data. The 2.1 M transistor chip is fabricated in a 2.0 V, 0.35 /spl mu/m, 3-layer metal CMOS process. It dissipates 0.5 W at 162 MHz/1.5 V and 1.1 W at 215 MHz/2.0 V.\",\"PeriodicalId\":117038,\"journal\":{\"name\":\"COMPCON '96. Technologies for the Information Superhighway Digest of Papers\",\"volume\":\"111 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-02-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"17\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"COMPCON '96. Technologies for the Information Superhighway Digest of Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CMPCON.1996.501767\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"COMPCON '96. Technologies for the Information Superhighway Digest of Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CMPCON.1996.501767","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 32-bit 162 MHz/215 MHz custom VLSI ARM microprocessor is described. The chip contains two 16 Kbyte, 32-way set associative caches for instructions and data. The 2.1 M transistor chip is fabricated in a 2.0 V, 0.35 /spl mu/m, 3-layer metal CMOS process. It dissipates 0.5 W at 162 MHz/1.5 V and 1.1 W at 215 MHz/2.0 V.
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