SRAM write assist techniques for low power applications

In modern System-on-Chip (SoC) large amount of area is occupied by memory circuits. Due to process variations in advanced CMOS technologies, the proper read and write operations of an 6T SRAM bitcell are the major issues. In this paper two write assist techniques - Word Line Overdrive (WLOD) and Negative Bitline (NBL), are discussed and compared. The idea presented here is that these techniques can be used for low power applications by reducing the supply voltage (VDD) with maintaining the write ability and read stability of the bitcell. Simulation results demonstrate enhanced write margin (WM) for the bitcell and stable operation at low VDD. These techniques are based on tuning the strength of the access transistor with respect to the pull-up transistor of the bitcell. The simulations are done using 45 nm CMOS technology with process variations taken along.