变频直流/交流变换器与EMI降低

Harreez M. Villaruz, W. Liou
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引用次数: 2

摘要

本文提出了一种结合扩频调频技术产生变频正弦信号的方法,用于抑制高开关频率引起的电磁干扰。这些都是通过Verilog硬件描述语言(Verilog HDL)实现的,并使用Quartus工具链在Altera DE2-70 FPGA板上合成,以满足低成本和灵活性的要求,并通过(1)Modelsim仿真,(2)Debussy仿真和(3)使用DAC7541进行实际数模转换来验证。为了实验验证,在生成的SPWM信号驱动下,对逆变器样机的输出进行了一系列测量。在输出SPWM处的测量结果表明,在50hz、60hz和70hz频率下,应用该技术可能会使THD分别增加0.092%、0.039%和0.087%,但它显著降低了至少12.8 dB的EMI峰值。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Variable frequency DC/AC converter with EMI reduction
This paper presents a way of generating a variable frequency sinusoidal signal in conjunction to the developed spread spectrum frequency modulation technique that is used to suppress the EMI caused by high switching frequencies. These are implemented through Verilog Hardware Descriptive Language (Verilog HDL) and synthesized on Altera DE2-70 FPGA board using Quartus tool chain to satisfy the low cost requirement and flexibility which are verified through (1) Modelsim simulations, (2) Debussy simulations and by (3) actual digital to analog conversion using DAC7541. For experimental validation, series of measurements are done on the output of the inverter prototype driven by the generated SPWM signal. Measurement results at the output SPWM show that the applied technique may have caused an increase in THD by 0.092% 0.039% and 0.087% at frequencies 50 Hz, 60 Hz and 70 Hz respectively, but it has significantly reduced the EMI peak with at least 12.8 dB.
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