{"title":"FPGA平台上不同处理器数量对H264的影响","authors":"O. Feki, H. Loukil, A. Ben Atitallah, N. Masmoudi","doi":"10.1109/SSD.2010.5585523","DOIUrl":null,"url":null,"abstract":"Multiprocessor architecture can be a solution to meet the increasing computational requirements for multimedia treatment algorithms such as video encoding. In this paper we study the effect of varying the processors number on resource utilization and system performance. We used Altera's NIOS II processors interconnected through Avalon bus. We vary the processors number from one to four and note its effect on the use of logic elements, DSP blocks and memory bits. We also note the change of the time execution of the Intra 16×16 chain of the H264/AVC encoder.","PeriodicalId":432382,"journal":{"name":"2010 7th International Multi- Conference on Systems, Signals and Devices","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Impact of varying processor number for H264 in FPGA platform\",\"authors\":\"O. Feki, H. Loukil, A. Ben Atitallah, N. Masmoudi\",\"doi\":\"10.1109/SSD.2010.5585523\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Multiprocessor architecture can be a solution to meet the increasing computational requirements for multimedia treatment algorithms such as video encoding. In this paper we study the effect of varying the processors number on resource utilization and system performance. We used Altera's NIOS II processors interconnected through Avalon bus. We vary the processors number from one to four and note its effect on the use of logic elements, DSP blocks and memory bits. We also note the change of the time execution of the Intra 16×16 chain of the H264/AVC encoder.\",\"PeriodicalId\":432382,\"journal\":{\"name\":\"2010 7th International Multi- Conference on Systems, Signals and Devices\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-06-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 7th International Multi- Conference on Systems, Signals and Devices\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SSD.2010.5585523\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 7th International Multi- Conference on Systems, Signals and Devices","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SSD.2010.5585523","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Impact of varying processor number for H264 in FPGA platform
Multiprocessor architecture can be a solution to meet the increasing computational requirements for multimedia treatment algorithms such as video encoding. In this paper we study the effect of varying the processors number on resource utilization and system performance. We used Altera's NIOS II processors interconnected through Avalon bus. We vary the processors number from one to four and note its effect on the use of logic elements, DSP blocks and memory bits. We also note the change of the time execution of the Intra 16×16 chain of the H264/AVC encoder.
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