A low-noise CMOS receiver frontend for MRI

In this paper a novel architecture for an integrated receiver front-end for micro magnetic resonance imaging (micro-MRI) applications is described. While the chip consumes only 9 mA supply current (4 mA in the LNA and 5 mA in the output buffer) from a 3.3 V power supply, it has a measured input referred noise density of only 0.6 nV/radic(Hz). The receiver consists of a reception coil, an on-chip tuning capacitor, a low-noise amplifier, and a 50 Omega output buffer. The system is designed for operation in a B0-field of 7 T corresponding to a frequency of 300 MHz. It is implemented in a 0.35 mum CMOS high-voltage process and occupies a chip area of 850 mum times 500 mum.