{"title":"基于Intel IPP的至强处理器雷达数字接收机的实现","authors":"Nune Divya, B. H. Chandana, D. Harika","doi":"10.1109/DISCOVER52564.2021.9663579","DOIUrl":null,"url":null,"abstract":"In this paper, the implementation of digital receiver using Intel IPP (Integrated Performance Primitives) library functions with digital filtering approach via fast convolution method is discussed using Xeon-processor, it can simulate more number of generated samples at the receiver using performance primitives by intel. The proposed work examines various benchmark functions in Intel IPP library to compute matched filter responses using time and frequency domain responses. Intel IPP executes multiple programs using SIMD (Single-Instruction Multiple Data) stream along with reducing computational time, cost and prolonged processor life time.","PeriodicalId":413789,"journal":{"name":"2021 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Implementation of Radar Digital Receiver based on Xeon-Processor using Intel IPP\",\"authors\":\"Nune Divya, B. H. Chandana, D. Harika\",\"doi\":\"10.1109/DISCOVER52564.2021.9663579\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, the implementation of digital receiver using Intel IPP (Integrated Performance Primitives) library functions with digital filtering approach via fast convolution method is discussed using Xeon-processor, it can simulate more number of generated samples at the receiver using performance primitives by intel. The proposed work examines various benchmark functions in Intel IPP library to compute matched filter responses using time and frequency domain responses. Intel IPP executes multiple programs using SIMD (Single-Instruction Multiple Data) stream along with reducing computational time, cost and prolonged processor life time.\",\"PeriodicalId\":413789,\"journal\":{\"name\":\"2021 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)\",\"volume\":\"50 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-11-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DISCOVER52564.2021.9663579\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DISCOVER52564.2021.9663579","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Implementation of Radar Digital Receiver based on Xeon-Processor using Intel IPP
In this paper, the implementation of digital receiver using Intel IPP (Integrated Performance Primitives) library functions with digital filtering approach via fast convolution method is discussed using Xeon-processor, it can simulate more number of generated samples at the receiver using performance primitives by intel. The proposed work examines various benchmark functions in Intel IPP library to compute matched filter responses using time and frequency domain responses. Intel IPP executes multiple programs using SIMD (Single-Instruction Multiple Data) stream along with reducing computational time, cost and prolonged processor life time.