The advantages and limitations of high level synthesis for FPGA based image processing

High level synthesis (HLS) tools can provide significant benefits for implementing image processing algorithms on FPGAs. The higher level (usually C based) representation enables algorithms to be expressed more easily, significantly reducing development times. The higher level also makes design space exploration easier, making it easier to optimise the trade-off between resources and processing speed. However, one danger of using HLS is simply porting existing image processing algorithms onto an FPGA platform. Often, better parallel or pipelined algorithms may be may be designed which are better suited to the FPGA architecture. Examples will be given from image filtering, to connected components analysis, to efficient memory management for 2-D frequency domain based filtering.