Energy Efficient Adiabatic Logic for Low Power VLSI Applications

This paper proposes a Adder circuit based on energy efficient two-phase clocked adiabatic logic. a simulative investigation on the proposed 1-bit full adder has been implemented with the proposed technique and thence compared with standard CMOS, Positive Feedback Adiabatic Logic (PFAL) and Two-Phase Adiabatic Static Clocked Logic (2PASCL) respectively. Comparison has shown a significant power saving to the extent of 70% in case of proposed technique as compared to CMOS logic in 10 to 200MHz transition frequency range.