A Novel Ternary D Flip-Flop using Pass Transistors based on GNRFET

For decades, computing logic uses Binary circuits based on CMOS technology. Ternary logic provides an edge over traditional Binary logic due to its ability to process more information content, thus reducing the Interconnection Count. In this paper, design of two Ternary D Latches based on GNRFET, are presented. Pass transistors along with STI gates are used to form the Ternary D latches (TDLs). These latches are cascaded in order to make Ternary D Flip-Flop (TDFF). The design is simulated on HSPICE, considering the three ribbon, 16-nm GNRFET model present on the Nanohub website. There is a considerable reduction in Transistor count as compared to the prevailing designs. Further, in our design, Propagation delay is also reduced significantly.