{"title":"低压FB-VDIBA及双路滤波器的设计与分析","authors":"S. Kumari, Maneesha Gupta","doi":"10.1109/SPIN.2018.8474200","DOIUrl":null,"url":null,"abstract":"In this work, a low voltage design of Fully Balanced Voltage Differencing Inverting Buffered Amplifier (FB-VDIBA) designed using dynamic threshold MOSFET (DTMOS). It consists of eight DTMOS transistors and rest all are traditional transistors. The transconductance and power dissipation of proposed FB-VDIBA are 1mS and 0.476mW respectively. The proposed circuit operates at ±0.4V supply voltage. To illustrate the validity of proposed FB-VDIBA, a voltage mode biquad filter is implemented. The natural frequency of biquad filter based on proposed FB-VDIBA is 7.9MHz. The FB-VDIBA and its biquad filter are implemented and simulated employing TSMC 180nm CMOS technology in Cadence tool.","PeriodicalId":184596,"journal":{"name":"2018 5th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A Design and Analysis of Low Voltage FB-VDIBA and Biquad Filter Application\",\"authors\":\"S. Kumari, Maneesha Gupta\",\"doi\":\"10.1109/SPIN.2018.8474200\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work, a low voltage design of Fully Balanced Voltage Differencing Inverting Buffered Amplifier (FB-VDIBA) designed using dynamic threshold MOSFET (DTMOS). It consists of eight DTMOS transistors and rest all are traditional transistors. The transconductance and power dissipation of proposed FB-VDIBA are 1mS and 0.476mW respectively. The proposed circuit operates at ±0.4V supply voltage. To illustrate the validity of proposed FB-VDIBA, a voltage mode biquad filter is implemented. The natural frequency of biquad filter based on proposed FB-VDIBA is 7.9MHz. The FB-VDIBA and its biquad filter are implemented and simulated employing TSMC 180nm CMOS technology in Cadence tool.\",\"PeriodicalId\":184596,\"journal\":{\"name\":\"2018 5th International Conference on Signal Processing and Integrated Networks (SPIN)\",\"volume\":\"51 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-02-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 5th International Conference on Signal Processing and Integrated Networks (SPIN)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SPIN.2018.8474200\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 5th International Conference on Signal Processing and Integrated Networks (SPIN)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SPIN.2018.8474200","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Design and Analysis of Low Voltage FB-VDIBA and Biquad Filter Application
In this work, a low voltage design of Fully Balanced Voltage Differencing Inverting Buffered Amplifier (FB-VDIBA) designed using dynamic threshold MOSFET (DTMOS). It consists of eight DTMOS transistors and rest all are traditional transistors. The transconductance and power dissipation of proposed FB-VDIBA are 1mS and 0.476mW respectively. The proposed circuit operates at ±0.4V supply voltage. To illustrate the validity of proposed FB-VDIBA, a voltage mode biquad filter is implemented. The natural frequency of biquad filter based on proposed FB-VDIBA is 7.9MHz. The FB-VDIBA and its biquad filter are implemented and simulated employing TSMC 180nm CMOS technology in Cadence tool.