{"title":"基于低功耗小面积旁路的乘法器设计","authors":"Amit Kumar Sahu, Laxmi Kumre","doi":"10.1109/ICICI.2017.8365186","DOIUrl":null,"url":null,"abstract":"Low power less area bypassing based multipliers proposed on the bases of modified XOR gate in low cost low power bypassing based multiplier. On the bases of different tested samples our proposed design has average 49.41% less area, 13.6% reduced power dissipation, 2.36% less delay and 20.89% less power delay product in comparison to different types of multiplier for 4×4 and 8×8 bit.","PeriodicalId":369524,"journal":{"name":"2017 International Conference on Inventive Computing and Informatics (ICICI)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Low-power less-area bypassing-based multiplier design\",\"authors\":\"Amit Kumar Sahu, Laxmi Kumre\",\"doi\":\"10.1109/ICICI.2017.8365186\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Low power less area bypassing based multipliers proposed on the bases of modified XOR gate in low cost low power bypassing based multiplier. On the bases of different tested samples our proposed design has average 49.41% less area, 13.6% reduced power dissipation, 2.36% less delay and 20.89% less power delay product in comparison to different types of multiplier for 4×4 and 8×8 bit.\",\"PeriodicalId\":369524,\"journal\":{\"name\":\"2017 International Conference on Inventive Computing and Informatics (ICICI)\",\"volume\":\"87 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 International Conference on Inventive Computing and Informatics (ICICI)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICICI.2017.8365186\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International Conference on Inventive Computing and Informatics (ICICI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICI.2017.8365186","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Low power less area bypassing based multipliers proposed on the bases of modified XOR gate in low cost low power bypassing based multiplier. On the bases of different tested samples our proposed design has average 49.41% less area, 13.6% reduced power dissipation, 2.36% less delay and 20.89% less power delay product in comparison to different types of multiplier for 4×4 and 8×8 bit.
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