基于主域的扭曲爱德华兹曲线点乘法的FPGA高速区域高效实现

N. Balan, B. Murugan
{"title":"基于主域的扭曲爱德华兹曲线点乘法的FPGA高速区域高效实现","authors":"N. Balan, B. Murugan","doi":"10.1109/icdcece53908.2022.9793323","DOIUrl":null,"url":null,"abstract":"On the digital side, data transfer is constantly subject to attack. A cypher strength study is an important part of any corporate or academic security assessment. A strong encryption mechanism is required for data security. For secure information transmission, System-On-Chips (SoCs) for Internet of things (IoT) applications require hardware-based coordinated arbitrary number generators. They don’t have a confined hardware and power spending plan, intends to the use of particular Twisted Edwards Curve (TEC). A symmetric encryption with incorporated TEC is proposed in this paper. A regular 40 nm CMOS innovation is utilized to accomplish the proposed plan. The aftereffects of the post-design recreation uncover that it gives great irregularity at a modest energy-per-bit cost. Moreover, the circuit finished all NIST assessments with no post-handling. When contrasted with the conventional encryption, it has an extremely low region increment of just 0.14 percent. As a proof of idea, a FPGA execution is likewise shown, which checks the simulated results. To show the double utilization of the proposed TEC, the Advanced Encryption Standard (AES) key extension method is also evolved. The AES technique depends solely on the substitute-permute network plan rule, and it functions admired in both programming and hardware. The procedure introduced here utilizes a solitary indistinguishable mystery key for encryption and disentangling. It can't be utilized in public sector or private, business, or different projects. The AES calculation is executed on two FPGAs in this research, and it was found that the Spartan-6 FPGA conveys better throughput and lower time delay than FPGA-based IoT gadgets.","PeriodicalId":417643,"journal":{"name":"2022 IEEE International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An High Speed Area Efficient Implementation of Prime Field based Twisted Edwards Curve Point Multiplication using FPGA Architecture\",\"authors\":\"N. Balan, B. Murugan\",\"doi\":\"10.1109/icdcece53908.2022.9793323\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"On the digital side, data transfer is constantly subject to attack. A cypher strength study is an important part of any corporate or academic security assessment. A strong encryption mechanism is required for data security. For secure information transmission, System-On-Chips (SoCs) for Internet of things (IoT) applications require hardware-based coordinated arbitrary number generators. They don’t have a confined hardware and power spending plan, intends to the use of particular Twisted Edwards Curve (TEC). A symmetric encryption with incorporated TEC is proposed in this paper. A regular 40 nm CMOS innovation is utilized to accomplish the proposed plan. The aftereffects of the post-design recreation uncover that it gives great irregularity at a modest energy-per-bit cost. Moreover, the circuit finished all NIST assessments with no post-handling. When contrasted with the conventional encryption, it has an extremely low region increment of just 0.14 percent. As a proof of idea, a FPGA execution is likewise shown, which checks the simulated results. To show the double utilization of the proposed TEC, the Advanced Encryption Standard (AES) key extension method is also evolved. The AES technique depends solely on the substitute-permute network plan rule, and it functions admired in both programming and hardware. The procedure introduced here utilizes a solitary indistinguishable mystery key for encryption and disentangling. It can't be utilized in public sector or private, business, or different projects. The AES calculation is executed on two FPGAs in this research, and it was found that the Spartan-6 FPGA conveys better throughput and lower time delay than FPGA-based IoT gadgets.\",\"PeriodicalId\":417643,\"journal\":{\"name\":\"2022 IEEE International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE)\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-04-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/icdcece53908.2022.9793323\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/icdcece53908.2022.9793323","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

在数字方面,数据传输不断受到攻击。密码强度研究是任何企业或学术安全评估的重要组成部分。为了保证数据的安全性,需要一个强大的加密机制。为了安全的信息传输,用于物联网(IoT)应用的片上系统(soc)需要基于硬件的协调任意数生成器。他们没有一个有限的硬件和电力支出计划,打算使用特殊的扭曲爱德华兹曲线(TEC)。本文提出了一种引入TEC的对称加密方法。利用常规的40纳米CMOS创新来完成所提出的计划。设计后重建的结果表明,它以适度的每比特能量成本提供了极大的不规则性。此外,电路完成了所有NIST的评估,没有后处理。与传统加密相比,它的区域增量极低,仅为0.14%。作为思想的证明,同样显示了FPGA执行,验证了模拟结果。为了显示所提出的TEC的双重利用,还发展了高级加密标准(AES)密钥扩展方法。AES技术仅依赖于替换-置换网络规划规则,在编程和硬件方面都具有良好的功能。这里介绍的程序使用一个孤立的不可区分的神秘密钥进行加密和解纠缠。它不能用于公共部门或私人,商业或其他项目。本研究在两个FPGA上执行AES计算,发现Spartan-6 FPGA比基于FPGA的物联网设备具有更好的吞吐量和更低的时间延迟。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An High Speed Area Efficient Implementation of Prime Field based Twisted Edwards Curve Point Multiplication using FPGA Architecture
On the digital side, data transfer is constantly subject to attack. A cypher strength study is an important part of any corporate or academic security assessment. A strong encryption mechanism is required for data security. For secure information transmission, System-On-Chips (SoCs) for Internet of things (IoT) applications require hardware-based coordinated arbitrary number generators. They don’t have a confined hardware and power spending plan, intends to the use of particular Twisted Edwards Curve (TEC). A symmetric encryption with incorporated TEC is proposed in this paper. A regular 40 nm CMOS innovation is utilized to accomplish the proposed plan. The aftereffects of the post-design recreation uncover that it gives great irregularity at a modest energy-per-bit cost. Moreover, the circuit finished all NIST assessments with no post-handling. When contrasted with the conventional encryption, it has an extremely low region increment of just 0.14 percent. As a proof of idea, a FPGA execution is likewise shown, which checks the simulated results. To show the double utilization of the proposed TEC, the Advanced Encryption Standard (AES) key extension method is also evolved. The AES technique depends solely on the substitute-permute network plan rule, and it functions admired in both programming and hardware. The procedure introduced here utilizes a solitary indistinguishable mystery key for encryption and disentangling. It can't be utilized in public sector or private, business, or different projects. The AES calculation is executed on two FPGAs in this research, and it was found that the Spartan-6 FPGA conveys better throughput and lower time delay than FPGA-based IoT gadgets.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信