The design of a multi-microprocessor based simulation computer - III

This paper presents further results in development of a discrete event simulation computer based on a network of micro processors. The network is being designed by identifying simulation tasks which may be performed in parallel with other computation required by the simulation, and then assigning those subtasks to attached processing elements in the network. The tasks of priority queue processing and state accounting are considered in this paper. A three attached processor simulation computer has been designed, using two processors for the event set and the third for state statistics accumulation. In a simulation model of this system, a forty to fifty percent reduction in the execution of a benchmark simulation program is easily achieved. (The benchmark program itself uses an adaptive scheduling algorithm). Further observations and suggestions for future research are presented.