{"title":"10Gb/s在线可扩展网络安全处理器阵列的设计","authors":"Yun Niu, Liji Wu, Jun Xu","doi":"10.1109/WOCC.2010.5510643","DOIUrl":null,"url":null,"abstract":"Design of a Gigabit In-Line scalable Network Security Processor on one chip is presented. With 8 parallel chips array and some control logic, the design may be used in 10 Gigabit Ethernet. Moreover, custom-specific off-chip crypto algorithms can replace the standard one on the chip through pr-reserved data interface, which improves the scalability of the design in crypto operation.","PeriodicalId":427398,"journal":{"name":"The 19th Annual Wireless and Optical Communications Conference (WOCC 2010)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of A 10Gb/s in-line scalable Network Security Processor array\",\"authors\":\"Yun Niu, Liji Wu, Jun Xu\",\"doi\":\"10.1109/WOCC.2010.5510643\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Design of a Gigabit In-Line scalable Network Security Processor on one chip is presented. With 8 parallel chips array and some control logic, the design may be used in 10 Gigabit Ethernet. Moreover, custom-specific off-chip crypto algorithms can replace the standard one on the chip through pr-reserved data interface, which improves the scalability of the design in crypto operation.\",\"PeriodicalId\":427398,\"journal\":{\"name\":\"The 19th Annual Wireless and Optical Communications Conference (WOCC 2010)\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-05-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"The 19th Annual Wireless and Optical Communications Conference (WOCC 2010)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/WOCC.2010.5510643\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"The 19th Annual Wireless and Optical Communications Conference (WOCC 2010)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/WOCC.2010.5510643","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of A 10Gb/s in-line scalable Network Security Processor array
Design of a Gigabit In-Line scalable Network Security Processor on one chip is presented. With 8 parallel chips array and some control logic, the design may be used in 10 Gigabit Ethernet. Moreover, custom-specific off-chip crypto algorithms can replace the standard one on the chip through pr-reserved data interface, which improves the scalability of the design in crypto operation.
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