一种降低光纤信道速度协商算法功耗的方法

Jie Jin, Dun Shan, X. Cui
{"title":"一种降低光纤信道速度协商算法功耗的方法","authors":"Jie Jin, Dun Shan, X. Cui","doi":"10.1109/ICSICT.2008.4735017","DOIUrl":null,"url":null,"abstract":"In this paper, we propose a simple but effective method to reduce the power in the design of the speed negotiation algorithm(SNA). Based on thoroughly analyzing the algorithm and the results of simulation, we identify the large timers, the most commonly used in the SNA, as the most power consuming parts. This paper further develops a partition algorithm to tackle the power issue of the large timers. Utilizing the proposed method, we can reduce the power by 30% as opposed to only 19% if directly applying clock-gating methodology. Combined with clock-gating methodology, we can get 38% reduction in power with no more than 5% increase in area.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A method to lower power in speed negotiation algorithm of fiber channel\",\"authors\":\"Jie Jin, Dun Shan, X. Cui\",\"doi\":\"10.1109/ICSICT.2008.4735017\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we propose a simple but effective method to reduce the power in the design of the speed negotiation algorithm(SNA). Based on thoroughly analyzing the algorithm and the results of simulation, we identify the large timers, the most commonly used in the SNA, as the most power consuming parts. This paper further develops a partition algorithm to tackle the power issue of the large timers. Utilizing the proposed method, we can reduce the power by 30% as opposed to only 19% if directly applying clock-gating methodology. Combined with clock-gating methodology, we can get 38% reduction in power with no more than 5% increase in area.\",\"PeriodicalId\":436457,\"journal\":{\"name\":\"2008 9th International Conference on Solid-State and Integrated-Circuit Technology\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-12-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 9th International Conference on Solid-State and Integrated-Circuit Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSICT.2008.4735017\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT.2008.4735017","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

在本文中,我们提出了一种简单而有效的方法来降低速度协商算法(SNA)的设计功耗。在深入分析算法和仿真结果的基础上,我们确定了SNA中最常用的大定时器是功耗最大的部分。本文进一步开发了一种分区算法来解决大型计时器的功耗问题。利用所提出的方法,我们可以减少30%的功率,而如果直接应用时钟门控方法,则只能减少19%的功率。结合时钟门控方法,我们可以在不超过5%的面积增加的情况下减少38%的功率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A method to lower power in speed negotiation algorithm of fiber channel
In this paper, we propose a simple but effective method to reduce the power in the design of the speed negotiation algorithm(SNA). Based on thoroughly analyzing the algorithm and the results of simulation, we identify the large timers, the most commonly used in the SNA, as the most power consuming parts. This paper further develops a partition algorithm to tackle the power issue of the large timers. Utilizing the proposed method, we can reduce the power by 30% as opposed to only 19% if directly applying clock-gating methodology. Combined with clock-gating methodology, we can get 38% reduction in power with no more than 5% increase in area.
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