A novel architecture for a high-performance network processing unit: Flexibility at multiple levels of abstraction

Network processing devices in future, high-speed network nodes have to be capable of processing several hundred million packets per second. Additionally, they have to be easily adaptable to new processing tasks due to the introduction of new services or protocols. Field programmable gate arrays (FPGAs) and network processors are suitable devices fulfilling these requirements: The former offer configurability at registertransfer level providing fine grain adaptability to unforeseen processing requirements and a high processing power. The latter are programmed at the more abstract software level and support high-speed execution of their fixed set of instructions. In this paper, we present a novel architecture for an FPGA-based highspeed network processing unit offering programmable modules at multiple levels of abstraction: register-transfer level, microcode level, software level and parameter level. A prototypical implementation demonstrates its feasibility with today's field programmable gate array devices offering a throughput of more than one hundred million minimum sized packets per second.