{"title":"CMOS缩放和非硅机会","authors":"Y. Nishi","doi":"10.1109/IWNC.2006.4570972","DOIUrl":null,"url":null,"abstract":"Scaling trend of CMOS, coupled with possibility of new channel materials, metal gate/ high k gate stack and source/drain structures is discussed, followed by several possibilities and opportunities for non-silicon devices including new material based non-volatile memory devices.","PeriodicalId":356139,"journal":{"name":"2006 International Workshop on Nano CMOS","volume":"71 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"CMOS scaling and non-silicon opportunities\",\"authors\":\"Y. Nishi\",\"doi\":\"10.1109/IWNC.2006.4570972\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Scaling trend of CMOS, coupled with possibility of new channel materials, metal gate/ high k gate stack and source/drain structures is discussed, followed by several possibilities and opportunities for non-silicon devices including new material based non-volatile memory devices.\",\"PeriodicalId\":356139,\"journal\":{\"name\":\"2006 International Workshop on Nano CMOS\",\"volume\":\"71 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 International Workshop on Nano CMOS\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWNC.2006.4570972\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 International Workshop on Nano CMOS","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWNC.2006.4570972","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Scaling trend of CMOS, coupled with possibility of new channel materials, metal gate/ high k gate stack and source/drain structures is discussed, followed by several possibilities and opportunities for non-silicon devices including new material based non-volatile memory devices.
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