163-180 GHz 2×2放大倍频阵列，峰值EIRP为+5 dBm

2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2013-06-02 DOI:10.1109/RFIC.2013.6569605

F. Golcuk, J. Edwards, B. Cetinoneri, Y. Atesal, Gabriel M. Rebeiz

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引用次数: 11

摘要

本文提出了一种采用45纳米CMOS SOI技术的2×2放大乘法器阵列，其片上天线频率为163-180 GHz。测量到的EIRP在165 ~ 175 GHz时> 2 dBm，在170 GHz时峰值为5 dBm，满足天线最严格的金属密度规则。放大器乘法器架构可扩展到N×M阵列，以实现高EIRP和发射功率。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 163–180 GHz 2×2 amplifier-doubler array with peak EIRP of +5 dBm

This paper presents a 2×2 amplifier-multiplier array with on-chip antennas at 163-180 GHz in 45 nm CMOS SOI technology. The measured EIRP is > 2 dBm at 165-175 GHz with a peak value of 5 dBm at 170 GHz meeting the stringiest metal-density rules for antennas. The amplifiermultiplier architecture is scalable to N×M arrays for high EIRP and transmit power.

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2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

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