Hierarchial clasterization, decomposition and multilevel macromodeling—the effective and efficient tools to solve the sigh and very high size combinatorial circuit type problems (abstract only)

The paper gives a generalization of author and his scientific group recent works in combinatorial non-polynomial high and very high size problems that appear in physical design automation of electronic devices including VLSI and SoC. The optimal circuit reduction method is marked as the better tool to recognize the hierarchical cluster structure of the circuit. Its possibilities to solve the wide spectrum of various problems, including forced hierarchical partitioning with given constraints, packaging, and placement are generalized. The common approach to these problems is developed on the basis of recursive using high quality algorithms of global and local optimization to the unique not high size task. The experiments confirm the high effectiveness of developed approach. For some well-known tests the optimal results were achieved at the first time and at some other cases the results were improved.