降低在高速测试应用过程中的功耗

Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2001-10-24 DOI:10.1109/DFTVS.2001.966760

Xiaowei Li, Huawei Li, Y. Min

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引用次数: 3

摘要

提出了一种在高速试验应用中降低功耗的方法。基于测试对序列的重新排序，测试过程中被测电路的开关活动可以最小化。定义测试对之间的汉明距离，以指导测试对的重新排序。它最大限度地减少了测试应用过程中的功耗，而不会减少延迟故障覆盖。实验结果表明，在测试应用过程中，功耗降低了84.69 ~ 98.08%。

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Reducing power dissipation during at-speed test application

Presents an approach to reducing power dissipation during at-speed test application. Based on re-ordering of the test-pair sequences, the switching activities of the circuit-under-test during test application can be minimized. Hamming distance between test-pairs is defined to guide test-pair re-ordering. It minimizes power dissipation during test application without reducing delay fault coverage. Experimental results are presented to demonstrate a reduction of power dissipation during test application in the range from 84.69 to 98.08%.

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Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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