B. Hwang, J. Kirchgessner, T. Bushey, S. Foertsch, J. Stipanuk, L. Marshbanks, J. Hernandez, E. Herald
{"title":"一种双极ECL静态RAM,多晶硅二极管负载存储单元采用单聚技术","authors":"B. Hwang, J. Kirchgessner, T. Bushey, S. Foertsch, J. Stipanuk, L. Marshbanks, J. Hernandez, E. Herald","doi":"10.1109/BIPOL.1988.51038","DOIUrl":null,"url":null,"abstract":"A 1 K*1 bipolar emitter coupled logic (ECL) static random access memory (RAM) using a polysilicon diode loaded memory cell is realised in a single poly bipolar process technology. The use of the polysilicon diode as the load element for the memory cell is made possible by the fact that its I-V characteristics exhibit an ideality factor of two. The hold voltage for the memory cell is larger than 240 mV over a wide range of cell currents with the lower bound residing in the sub- mu A range. Results show extremely stable operation against row select sensitivity. A 1.5-ns row address access time has been obtained from the test circuit.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A bipolar ECL static RAM with polysilicon diode loaded memory cell using single poly technology\",\"authors\":\"B. Hwang, J. Kirchgessner, T. Bushey, S. Foertsch, J. Stipanuk, L. Marshbanks, J. Hernandez, E. Herald\",\"doi\":\"10.1109/BIPOL.1988.51038\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 1 K*1 bipolar emitter coupled logic (ECL) static random access memory (RAM) using a polysilicon diode loaded memory cell is realised in a single poly bipolar process technology. The use of the polysilicon diode as the load element for the memory cell is made possible by the fact that its I-V characteristics exhibit an ideality factor of two. The hold voltage for the memory cell is larger than 240 mV over a wide range of cell currents with the lower bound residing in the sub- mu A range. Results show extremely stable operation against row select sensitivity. A 1.5-ns row address access time has been obtained from the test circuit.<<ETX>>\",\"PeriodicalId\":302949,\"journal\":{\"name\":\"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-09-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BIPOL.1988.51038\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BIPOL.1988.51038","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A bipolar ECL static RAM with polysilicon diode loaded memory cell using single poly technology
A 1 K*1 bipolar emitter coupled logic (ECL) static random access memory (RAM) using a polysilicon diode loaded memory cell is realised in a single poly bipolar process technology. The use of the polysilicon diode as the load element for the memory cell is made possible by the fact that its I-V characteristics exhibit an ideality factor of two. The hold voltage for the memory cell is larger than 240 mV over a wide range of cell currents with the lower bound residing in the sub- mu A range. Results show extremely stable operation against row select sensitivity. A 1.5-ns row address access time has been obtained from the test circuit.<>