{"title":"具有多频率可调元件的便携式嵌入式系统系统级细粒度动态电压和频率缩放","authors":"Ku He, Yibo Chen, Rong Luo","doi":"10.1109/PORTABLE.2007.56","DOIUrl":null,"url":null,"abstract":"This paper presents a system level dynamic voltage and frequency scaling (DVFS) technique targeted toward non realtime applications running on a portable embedded system with multiple frequency-adjustable components. The key idea is to balance the frequency of processor core and memory. Some applications may be I/O bound, some may be CPU bound, and the others may be Memory bound. The proposed DVFS technique relies on pre-collected statistical information of different applications to calculate the expected workload for each coming time slice, and then, it adjusts the frequency of processor core, memory, and system bus to meet the timing constraints(with acceptable penalty) and achieves the maximum energy saving. The proposed technique has been tested on the PXA27x (XScale based) [8] embedded platform and the result was exciting, the processor energy saving can achieve up to 70% in memory bound applications, and the timing performance degradation was less than 5%. In CPU bound applications, the energy saving is relatively small, about 20~40%.","PeriodicalId":426585,"journal":{"name":"2007 IEEE International Conference on Portable Information Devices","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A System Level Fine-Grained Dynamic Voltage and Frequency Scaling for Portable Embedded Systems with Multiple Frequency Adjustable Components\",\"authors\":\"Ku He, Yibo Chen, Rong Luo\",\"doi\":\"10.1109/PORTABLE.2007.56\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a system level dynamic voltage and frequency scaling (DVFS) technique targeted toward non realtime applications running on a portable embedded system with multiple frequency-adjustable components. The key idea is to balance the frequency of processor core and memory. Some applications may be I/O bound, some may be CPU bound, and the others may be Memory bound. The proposed DVFS technique relies on pre-collected statistical information of different applications to calculate the expected workload for each coming time slice, and then, it adjusts the frequency of processor core, memory, and system bus to meet the timing constraints(with acceptable penalty) and achieves the maximum energy saving. The proposed technique has been tested on the PXA27x (XScale based) [8] embedded platform and the result was exciting, the processor energy saving can achieve up to 70% in memory bound applications, and the timing performance degradation was less than 5%. In CPU bound applications, the energy saving is relatively small, about 20~40%.\",\"PeriodicalId\":426585,\"journal\":{\"name\":\"2007 IEEE International Conference on Portable Information Devices\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-05-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE International Conference on Portable Information Devices\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/PORTABLE.2007.56\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE International Conference on Portable Information Devices","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PORTABLE.2007.56","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A System Level Fine-Grained Dynamic Voltage and Frequency Scaling for Portable Embedded Systems with Multiple Frequency Adjustable Components
This paper presents a system level dynamic voltage and frequency scaling (DVFS) technique targeted toward non realtime applications running on a portable embedded system with multiple frequency-adjustable components. The key idea is to balance the frequency of processor core and memory. Some applications may be I/O bound, some may be CPU bound, and the others may be Memory bound. The proposed DVFS technique relies on pre-collected statistical information of different applications to calculate the expected workload for each coming time slice, and then, it adjusts the frequency of processor core, memory, and system bus to meet the timing constraints(with acceptable penalty) and achieves the maximum energy saving. The proposed technique has been tested on the PXA27x (XScale based) [8] embedded platform and the result was exciting, the processor energy saving can achieve up to 70% in memory bound applications, and the timing performance degradation was less than 5%. In CPU bound applications, the energy saving is relatively small, about 20~40%.