High conversion gain receiver for wireless sensor network

This work demonstrates a fully integrated 24 GHz CMOS receiver for high gain and wireless sensor network. The receiver incorporates a low noise amplifier, double-balanced mixer and an active balun for single to differential. This mixer designs with active load to decrease power dissipation. To increase mixer gain, an inductor is added to eliminate parasitic capacitances at the load of input transistor. The fabricated chip has been implemented in a 0.18 μm CMOS technology. The measurement shows that the receiver demonstrates following performances: power conversion gain of 35 dB at 23.5GHz, noise figure of 7.6 dB, input power at 1 dB compression point of -38 dBm and IIP3 of -29 dBm. The receiver chip consumes 57.84mW from a 1.8 V power supply, the dissipated power is with 25.56mW for the LNA, 22.68mW for the active balun, 9.6mW for the mixer and output IF buffer.