逻辑设计中虚拟实验室的开发

B. Evstatiev, N. Evstatieva, Dimitar Trifonov
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引用次数: 1

摘要

本研究以虚拟电气工程设备引擎(EVEEE)为工具,开发“逻辑设计”课程的虚拟实验室。基本逻辑门(AND, OR, NAND, NOR, NOT)和组合逻辑(解码器和多路复用器)被建模为模拟设备,具有输入和输出。每个输入用1 MΩ电阻表示,每个输出是一个非线性依赖源,都连接到地。依赖源的逻辑使用SPICE的条件逻辑实现。为了提高逻辑电路的可追溯性,每个输入/输出插座都有一个相应的虚拟发光二极管,可以可视化其状态——数字1或数字0。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Development of a Virtual Laboratory in Logic Design
In this study is presented the development of a virtual laboratory for the "Logic design" course, using the Engine for Virtual Electrical Engineering Equipment (EVEEE). The basic logic gates (AND, OR, NAND, NOR, NOT) and combinational logic (decoder and multiplexer) are modeled as analog devices, with inputs and outputs. Each input is represented with a 1 MΩ resistor, and each output is a nonlinear dependent source, both connected to ground. The logic of the dependent source is implemented using SPICE’ conditional logic. To improve the traceability of the logic circuit, each input/output socket has a corresponding virtual light emitting diode, which visualizes its state – digital one or digital zero.
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