{"title":"14.4-GS/s, 5位，50mW时间交错ADC，具有分布式跟踪保持和采样即时同步，用于基于ADC的SerDes","authors":"Tao Jiang, P. Chiang","doi":"10.1109/IEEE-IWS.2015.7164567","DOIUrl":null,"url":null,"abstract":"A 14.4-GS/s 5-b ADC is designed in 40nm CMOS with eight time-interleaved channels of Flash/Successive-Approximation hybrid sub-ADCs each running at 1.6GS/s. A modified bootstrapped track-and-hold switch incorporates a global clock to synchronize the sampling instant of each individual sub-channel, therefore improving multi-phase alignment. Measurement results show that the ADC can achieve a peak SNDR of 26.5dB, consuming 49.4mW, leading to a FoM of 199fJ/conversion-step, in a core area less than 800μm by 500μm.","PeriodicalId":164534,"journal":{"name":"2015 IEEE International Wireless Symposium (IWS 2015)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"14.4-GS/s, 5-bit, 50mW time-interleaved ADC with distributed track-and-hold and sampling instant synchronization for ADC-based SerDes\",\"authors\":\"Tao Jiang, P. Chiang\",\"doi\":\"10.1109/IEEE-IWS.2015.7164567\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 14.4-GS/s 5-b ADC is designed in 40nm CMOS with eight time-interleaved channels of Flash/Successive-Approximation hybrid sub-ADCs each running at 1.6GS/s. A modified bootstrapped track-and-hold switch incorporates a global clock to synchronize the sampling instant of each individual sub-channel, therefore improving multi-phase alignment. Measurement results show that the ADC can achieve a peak SNDR of 26.5dB, consuming 49.4mW, leading to a FoM of 199fJ/conversion-step, in a core area less than 800μm by 500μm.\",\"PeriodicalId\":164534,\"journal\":{\"name\":\"2015 IEEE International Wireless Symposium (IWS 2015)\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-07-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE International Wireless Symposium (IWS 2015)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEEE-IWS.2015.7164567\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Wireless Symposium (IWS 2015)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEEE-IWS.2015.7164567","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
14.4-GS/s, 5-bit, 50mW time-interleaved ADC with distributed track-and-hold and sampling instant synchronization for ADC-based SerDes
A 14.4-GS/s 5-b ADC is designed in 40nm CMOS with eight time-interleaved channels of Flash/Successive-Approximation hybrid sub-ADCs each running at 1.6GS/s. A modified bootstrapped track-and-hold switch incorporates a global clock to synchronize the sampling instant of each individual sub-channel, therefore improving multi-phase alignment. Measurement results show that the ADC can achieve a peak SNDR of 26.5dB, consuming 49.4mW, leading to a FoM of 199fJ/conversion-step, in a core area less than 800μm by 500μm.
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